Enabling nanoelectronics and nanoscale processing techniques in carbon
Surrey NanoSystems has developed a suite of fundamental techniques to support the precise growth of very high density, low defect, carbon based nanomaterial structures at low temperatures in critical CMOS compatible environments. These NanoGrowth® grown class of materials have been developed for use as a replacement for the leading copper damascene interconnect technology currently in mainstream use. Adopted in the 90’s, copper damascene Back End of Line (BEOL) ‘VIA’ processes is facing real challenges due to chip geometry shrinks and material physics. Global industry experts and the ITRS roadmap see major challenges to copper in BEOL interconnects and VIAs below the industries 22nm technology node.
Surrey NanoSystems Patented technologies already address many of the key challenges to replacing copper with carbon nanomaterials in next generation silicon processing
These techniques are applied while simultaneously maintaining the temperature of the underlying substrate - with its CMOS gate structures - well below 400 degrees C to avoid thermal and stress damage to the front and back end structure. The patented techniques include:
Top-down 'tuned' IR energy delivery that provides catalyst activation and materials growth directly where it's needed and avoids agglomeration of nano catalyst nucleation sites - almost instantly 'freezing' catalyst islands in place and maintaining very high density growth
IR/UV tuned thermal barrier films used to concentrate growth energy in the catalyst and not the underlying substrate
Adaptive substrate cooling with dynamic control throughout nanomaterial processing stage - keeps the silicon, ILD and interconnects at a low stress, structure compatible temperature, and allows a stable steady state growth step
- Creation and embedding of catalytic nanoparticles - enabling size selectivity, density and alloy composition control whilst removing the need for high temperature catalyst film anneals used in the conventional approach to carbon nanotube VIA formation
- 'In growth' purification techniques to ensure reliable and repeatable results - no build up of a:C to poison the process, increase VIA resistivity and stress - leading to a repeatable end result
These fundamental techniques provide an enabling technology for applying carbon nanomaterials technology to future silicon device fabrication, and Surrey NanoSystems seeks relationships with partners who have the know-how in allied areas including damascene interconnects, TiN/TaN/Ru liners, ECD, ALD and CMP, to make these technologies available in practical forms to the semiconductor fabrication industry.
SEM Images of carbon nanotubes grown by the NanoGrowth LT process at temperatures below 350°C (LH) and 370°C (RH)
Link to publication on CNT grown <350°C in the Journal 'Carbon'
Link to publication on PTCVD grown tubes <370°C in the journal 'Nanotechnology'
Novel room-temperature catalyst deposition and top-down energy delivery coupled with advanced thermal control of the substrate, provide key advantages for growing dense nanomaterial structures in back end of line (BEOL) silicon processes.
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